The H.265 HEVC Decoder System IPr is a highly optimized and parameterisable IP Core targeted exclusively at Intel FPGA technology. It is an ultra-low latency solution that is extremely robust with excellent error concealment, compliant with the ITU-T H.265 standard, designed for applications ranging from High End Broadcast, Contribution and Medical applications through to consumer grade applications.
Korusys provide both the IP core and, as an Intel FPGA Design Solutions Network Partner, experienced Design Services surrounding the core to implement the most efficient solution for each customer application. The IPr can be provided as a standalone netlist solution for integration into a customer’s design, or it can be customized and scaled to a particular implementation. A simple API is provided to ease integration.
This IPr is available as just the IP Core or as a package with our High Performance FPGA PCIe Accelerator Card.
- Complete stand-alone FPGA solution
- Ultra low latency
- High quality and High precision
- Fully standards compliant, tested with ITU-T conformance streams and bit accurate to HM reference model.
- Provided as IP core or wrapped in custom design as per customer requirements.
- Simple API provided to ease integration.
- Extremely Robust with excellent Error Concealment.
- Standard : H.265 HEVC
- Profiles : Main 4.1 / Main 5.0
- Resolutions : Up to 4k
- Frame Rate : 60 fps at HD and UHD
- Chroma : 4:2:2 or 4:2:0
- Precision : 8, 10, 12 or 16 bit
- FPGA : Arria10, StratixV, CycloneV
Block Diagram of the H.265 HEVC Decoder IP Core