The HARD_TEMAC described in this document has been designed incorporating the applicable features described in IEEE Std. 802.3-2002. Differences between that specification and the Xilinx HARD_TEMAC implementation are highlighted and explained in the Specification Exceptions section. The HARD_TEMAC is an intellectual property (IP) soft core designed for implementation in a Virtex-4 FX FPGA.
- Filtering of “bad” receive frames to reduce processor bus utilization.
- Hardware selectable DCR or PLB host interface to configuration registers.
- GMII and MII interfaces to external PHY devices.
- SGMII supported through MGT interface to external copper PHY layer.
- Complies with IEEE 802.3-2000 specification.
- Full duplex operation.
- Media Independent Interface Management (MIIM) for access to PHY transceiver registers.