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130nm FTP Non Volatile Memory for Standard CMOS Logic Process
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Hash Crypto Engine
With a flexible wrapper supporting a wide selection of programmable hashing modes (SHA-1, SHA-224, SHA-256, SHA-384, SHA-512 and MD-5) and several options of data interface, the Hash crypto core is an easy-to-use solution with predictable resources and performances on ASIC and FPGA.
Features
- ASIC and FPGA
- Supports:
- SHA-1
- SHA-224
- SHA-384
- SHA-512
- SM3
- MD5
- Supports HMAC
- Message padding in software or hardware
- Low power feature
- Data interface: AMBA (AHB/AXI) with optional DMA
- AMBA (APB, AXi-4 Lite) Configuration Interface
- Control interface: APB/AXI4-lite
Benefits
- Off-the-shelf, predictable and silicon-proven solution
- Logic footprint optimized to used hash functions
- Supports several hash functions
- Easy to integrate
- User-friendly Software API
- Portable and optimized to ASIC or FPGA technology
Deliverables
- Netlist or RTL
- Scripts for synthesis
- Self-checking Testbench based on FIPS vectors
- Datasheet
- Integration guide
Applications
- Digital signature
- Key derivation
Block Diagram of the Hash Crypto Engine IP Core
View Hash Crypto Engine full description to...
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