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HBM Subsystem IP Gen2
Open-Silicon’s HBM IP is the industry’s first comprehensive solution for integrating high-bandwidth memory into ASICs thereby achieving the ultimate high performance and low power. By integrating the HBM protocol controller, PHY and IO into one sub-system IP product, interoperability aspects between the different system components are addressed. As an early advocate of 2.5D and 3D ASIC design technologies and by leveraging its experience from the industry’s first successful 2.5D SoC SiP demonstration, Open-Silicon plays a key role in enabling industry applications to leverage the HBM 3D-stacked DRAM technology.
Features
- HBM Controller: JEDEC HBM Gen2 DRAM Specification compliant
- Supports up to 2 Gbps per pin data rate
- Configurable Independent HBM Channel support
- Low latency operation
- HBM PHY: Ultra-low latency
- Coarse and Fine grain IO training
- Low power HBM memory and PHY modes
- Loopback support for Testability
- CMOS IO with programmable drive strengths
- 2Gbps/1Ghz DDR with light output loading
Benefits
- Comprehensive HBM IP solution that includes the HBM controller, HBM PHY and HBM custom-die-to-die I/Os
Deliverables
- HBM Controller: Synthesizable RTL
- HBM PHY and IO Delivery as single Hardened IP Block
- GDS II (Micro bump Included)
- Verilog Models for Simulations
- Documentation
Applications
- Communication, Networking, High Performance Computing, Imaging, Video
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