HBM2E PHY for TSMC N5
The DesignWare HBM2/HBM2E PHY is ideal for systems with low to modest memory capacity that require higher bandwidth than is attainable with practical DDR4-based systems. The DesignWare HBM2/HBM2E PHY is provided as a set of hard macrocells delivered as GDSII. These hard macrocells include integrated application-specific HBM2/HBM2E I/Os required for HBM2/HBM2E signaling. The design is optimized for high performance, low latency, low area, low power, and ease of integration. The hard macrocells are easily assembled into a complete 1024-bit HBM2/HBM2E PHY. The RTL-based PHY Utility Block (PUB) supports the GDSII-based PHY components and includes the PHY training circuitry, configurations registers and BIST control. The HBM2/HBM2E PHY includes a DFI 4.0-compatible interface to the memory controller, supporting 1:1 and 1:2 clock ratios. The design is compatible with both metal-insulator-metal (MIM) and non-MIM power decoupling strategies.
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