HBM3/3E PHY & Controller

This document describes a general layout scheme and Innosilicon HBM3/3E PHY connecting to the controller using a DFI digital interface. All interface timing is in 1X SDR clock domain. This interface is flexible and can be converted to any customer desired format and timing sequence. The PHY to controller interface is running at single data rate (SDR) therefore read/write bus is double width.

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