HDCP 2.3 Transmitter core is compliant with standard HDCP specification as 2.2 and 2.3. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. HDCP 2.3 Transmitter IIP is proven in FPGA environment. The Transmitter interface of the HDCP can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
- Implemented in Unencrypted Verilog, VHDL and SystemC
- Supports HDMI Specification 1.4b and 2.0b compliant.
- Supports High-bandwidth Digital Content Protection (HDCP)v1.4 and v2.2
- Supports CEA-861-F
- Full HDMI source device and sink device functionality.
- Supports Video data coding.
- Supports TERC4 coding and Control period codings.
- Supports Serialization and de-serialization.
- Supports three operating modes given below,
- -> Video period
- -> Data Island period
- -> Control period
- Supports display data channel(DDC)
- Supports 3D, 4K x 2K Resolution, Expanded Color Spaces and Audio Return Channel
- Supports all packet formats in HDMI Specification 1.4b and 2.0b compliant
- Supports data island error correction(ECC).
- Supports Consumer Electronics Control (CEC )
- Supports HDMI Ethernet and Audio Return Channel (HEAC)
- Supports Serial and Symbol interfaces
- Status counters for various events on bus.
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- The HDCP 2.3 Transmitter interface is available in Source and netlist products.
- The Source product is delivered in plain text verilog. If needed VHDL,SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.