HDMI 2.0 Receiver IP in TSMC40LP

Features

• - Clock range : 25-600MHz
• - Built in Low-jitter PLL
• - PADS cell includes ESD protection circuit
• - Built in termination resistor

Deliverables

• Link in RTL code and PHY GDS2 at foundry merge; documentations included Link and PHY specifications, SoC integration guildlines & board level design guildlines to pass HDMI certification

• see the entire HDMI 2.0 Receiver IP in TSMC40LP datasheet
• get in contact with HDMI 2.0 Receiver IP in TSMC40LP Supplier