HDMI 2.0 Receiver IP

Features

• - 4K2K/60Hz resolution support
• - HDCP1.4/2.2 support
• - 3D format(Frame Packing/Side-by-Side Half/Top & Bottom) support
• - Video Output Interface
• Support CEA-861D/VESA DMT(*1) video format
• 16bit : YCbCr422 (8bit x 2)
• 20bit : YCbCr422 (10bit x 2)
• 24bit : YCbCr422 (12bit x 2), RGB/YCbCr444 (8bit x 3)
• 30bit : RGB/YCbCr444 (10bit x 3)
• 36bit : RGB/YCbCr444 (12bit x 3)
• - Audio Output Interface
• 3 wired serial interface(I2S/left justified/right justified) LPCM: 8 ch
• DSD: 8 ch, HBR compliant
• IEC 60958/IEC 61937 compliant
• - Color space conversion support
• ITU-R BT.601/709/2020 Non Const/RGB Full/RGB Limit/xvYCC
• (Not support with ITU-R BT.2020 Const)
• - YCbCr420 to YCbCr422 conversion support
• - TMDS Deep color support
• 8/10/12bit (*2)
• - CEC
• CEC hard engine support

Deliverables

• Link in RTL code and PHY GDS2 at foundry merge; documentations included Link and PHY specifications, SoC integration guildlines & board level design guildlines to pass HDMI certification

• see the entire HDMI 2.0 Receiver IP datasheet
• get in contact with HDMI 2.0 Receiver IP Supplier