The HDMI (High Definition Multimedia Interface) TX PHY core is compatible with the HDMI v1.4 / v2.0 spec.
The HDMI TX PHY core supports 1080p video resolution including deep-color mode, 3D, and 4K x 2K video format.
The HDMI TX PHY core can generate both pixel clock and TMDS clock from a reference clock, which eliminate a need for separate pixel clock generator in an SOC. HDMI TX PHY core also support loop-back test using pattern generator/comparer.
For deep color mode, the HDMI TX PHY core supports all pixel clock frequencies specified in HDMI specifications with 1.25X and 1.5X TMDS clocks.
- Samsung Foundry 14nm low power CMOS device technology
- 1.8V, 0.8V dual power supply
- Compliant to HDMI 2.0 specification
- Supports 25MHz to 594MHz TMDS clock
- Supports internal loop-back for low cost at-speed test
- Supports programmable analog characteristics through JTAG, APB register control
- 60-bit CMOS interface with LINK logic for relaxed timing constraint between LINK and PHY
- Integrated pixel clock generator
- Supports on-chip source termination
- Front-end: Timing LIB, Verilog model, Sample test bench
- Back-end: Physical view LEF, GDSII layout, DRC, LVS
- Documentation : Datasheet and User’s guide
Block Diagram of the HDMI 2.0 TX PHY, 6.0 Gbps (71152) IP Core