The HDMI 2.0 Compliant Phy supports up to 18gbps bit rate and enables to 4Kx2K resolution at 60Hz frame rate. It receives three streams (3x6Gbps) of 10-bit transition minimized data as input along with synchronous TMDS clock. It serializes and transmits them in differential form over three channels. The clock is also transmitted along with the data as a differential signal according to the specifications laid out in the Chapter “Electrical Characteristics” of the HDMI Standard specification of the Transmitter. This block consists of high speed serializer and output differential buffers along with the differential output pads and power supplies required by the block. The electrical layer can work over the TMDS clock range from 25MHz to 600MHz. It can be customized process nodes from multiple foundries.