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HDMI 2.1 eARC Tx PHY in TSMC (16nm, 12nm)
The Synopsys DesignWare® HDMI 2.1 TX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the necessary logic to implement and verify designs for various HDMI-based applications. The IP provides quality digital video and audio transmission with up to 48Gbps aggregate bandwidth for uncompressed 8K resolution at 60Hz refresh rate. It supports key features of HDMI 2.1 including dynamic HDR and enhanced audio return channel (eARC), ensuring higher frameby-frame video quality and most advanced audio formats.
The complete power- and area-optimized HDMI 2.1 TX IP solution encompasses a suite of configurable digital controllers, high-speed, mixed-signal PHY IP, verification IP, High-Bandwidth Digital Camera Protection (HDCP) IP, IP Prototyping Kits, Linux software drivers, and subsystem. Having all necessary design blocks for the HDMI subsystem, the IP solution enables system-on-chip (SoC) designers to lower integration risk and accelerate time-to-market.
The complete power- and area-optimized HDMI 2.1 TX IP solution encompasses a suite of configurable digital controllers, high-speed, mixed-signal PHY IP, verification IP, High-Bandwidth Digital Camera Protection (HDCP) IP, IP Prototyping Kits, Linux software drivers, and subsystem. Having all necessary design blocks for the HDMI subsystem, the IP solution enables system-on-chip (SoC) designers to lower integration risk and accelerate time-to-market.
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