The HDMI Forward Error Correction (FEC) Receiver IP Core implements Reed-Solomon FEC and symbol de-interleaving/de-mapping as specified by the HDMI 2.1 specification.
Forward Error Correction is required to ensure glitch-free operation in Fix Rate Lane (FRL) mode, a packet mode introduced in HDMI 2.1. FRL allows for the use of Display Stream Compression (DSC) bitstream transport.
- HDMI 2.1 compliant
- Reed-Solomon RS(255,251) FEC, 8-bit symbols
- Supports 3-lane and 4-lane operation
- Includes error counters
- Hardent’s IP portfolio offers customers ready-made solutions to accelerate product development and meet demanding time-to-market schedules. Developed by our team of experienced FPGA and ASIC designers, our IP products have undergone extensive verification and offer proven interoperability and compatibility.
- Encrypted RTL source code IP core
- Functional and structural coverage reports
- Comprehensive integration guide
- Technical support and maintenance updates
- UHD monitors
- UHD TVs & home theaters
- HDMI 2.1 hubs & accessories
- Professional video equipment
Block Diagram of the HDMI 2.1 Forward Error Correction (FEC) Receiver