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CLICK - The universal solution of power gating for the whole SoC
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HDMI ver1.3 Receiver IP
HDMI Receiver Link IP Core supporting the standard of HDMI 1.3a, which will be quickly implemented into SoC of consumers; product (HD-TV, AV receiver... etc.). The best performance, efficiency and characteristic of HDMI Receiver Link IP can be realized when it is connected to HDMI Receiver PHY IP. This HDMI Rx IP can be customized to meet customer specific requirement.
Features
- COMPLAINT WITH:
- HDMI 1.3a
- DVI 1.0
- EIA/CEA-861D
- HDCP 1.2
- DIGITAL VIDEO OUTPUT
- Digital TV resolution - 480i, 576i, 480p, 576p, 720p, 1080i, 1080p
- PC resolution - VGA, XGA, SXGA, WSXGA, UXGA
- RGB, YCbCr digital video format
- 12bit RGB/YCbCr 4:4:4
- 16/20/24bit YCbCr 4:2:2
- 8/10/12bit YCbCr 4:2:2 (ITU.601 and 656)
- Programmable 2-way color space converter
- YCbCr <-> RGB
- Deep color supported up to 16bit per pixel
- Support xvYCC
- All Packets including Gamut Metadata Packet are receivable
- DIGITAL AUDIO OUTPUT
- Standard SPDIF for stereo or compressed audio up to 192KHz
- PCM, Dolby Digital, DTS Digital Audio transmission through I2s up to 8 channel
- IEC60958 or IEC61937 compatible
- DSD (Direct Stream Digital) format for 1 bit Audio/SACD
- High Bit Rate Compressed Audio (DTS HD master audio/Dolby True digital)
- CONTENT PROTECTION
- Built-in High-bandwidth Digital Content Protection (HDCP) encryption engine
- Authenticate up to 2 receivers and repeaters with maximum cascade of 7
- Support Advanced Cipher Mode
- Support Enhanced Link Verification
Deliverables
- Configurable RTL Code
- HDL based test bench and behavioral models
- Test cases
- Protocol checkers, bus watchers and performance monitors
- Configurable synthesis shell
- Documentation
- Design Guide
- Verification Guide
- Synthesis Guide
Block Diagram of the HDMI ver1.3 Receiver IP IP Core
View HDMI ver1.3 Receiver IP full description to...
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