The Hardware Encoder Video Accelerator (HEVA), supports HEVC encoding low complexity with a flexible architecture targeting at least 1080p60 with minimal processing units and memory cuts, and up to 2160p120 with large number of units and large memory cuts.
Trade-off performance/area at design configuration
– Reference cache size for 2160p30 at 350 MHz, 1 reference frame and bandwidth
– overhead of 100% for references i.e. 1.5 GBytes/sec (minimal is 1.2 GB/s)
Host interface AXI3/AXI4 slave interface for the registers and command/status FIFO
Memory interface AXI3/AXI4 Streaming interfaces to External DRAM
– Asynchronous AXI3/AXI4 128 bits interface
– Synchronous DMA arbiter and memory interface
Task sequencing modules
– Manages communication and storage between processing modules
– Control the shared memories and caches between the TPU modules and TSU/MIF
– Defines the execution mode of the task processing units
Task processing modules
– Perform the pixel and bit-stream processing under control of TCR/TSU
– The number of processing elements is defined at design configuration to sustain the required performance.
– A local reference cache is needed for performance for some processing units.