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HEVC 4Kp60 Decoder, Supports 4:2:2, 10-bit decoding and 150Mbps bitrate
VYUsync’s HEVC 4Kp60, 4:2:2, 10-bit Decoder Core is a highly optimized universal video decompression engine. The Decoder has been tested with more than 3000 industry standard test streams and is compatible with any ASIC/FPGA/Software encoders in the market. It is a sub frame latency decoder with lowest delay of 5 – 8 mili seconds for 4Kp60 Decode. The decoder has been proven on the field and trusted by leaders in the Broadcast Industry.
It is well suited for various applications ranging from broadcast and professional video to high end consumer electronics. The decoder design is fully autonomous and does not require any external processor to aid the decode operation. The IO interface comprises of an input FIFO and an output frame buffer. Decoded data can also be provided on a serial bus with embedded sync information. The decoder requires DDR SDRAM to store reference pictures. The decoder solution is available either as a FPGA netlist or in source code format and can be customized to meet the requirements of end users.
It is well suited for various applications ranging from broadcast and professional video to high end consumer electronics. The decoder design is fully autonomous and does not require any external processor to aid the decode operation. The IO interface comprises of an input FIFO and an output frame buffer. Decoded data can also be provided on a serial bus with embedded sync information. The decoder requires DDR SDRAM to store reference pictures. The decoder solution is available either as a FPGA netlist or in source code format and can be customized to meet the requirements of end users.
Features
- Standard: HEVC/H.265 ( ISO/ IEC 23008-2 and ITU-T H.265 )
- Profiles: Main, Main10, Main 12, Main 10 4:2:2 and Main 12 4:2:2
- Video Resolutions: Up to 4096 x 2160
- Frame Rate: 60 fps
- Bit rate: 150Mbps. Scalable
- Chroma Format: Monochrome, 4:2:0 & 4:2:2
- Precision: Bit depths from 8 to 12
- Input Format: Elementary or Transport stream
- Output Format: Decoded pictures in frame buffer. Optional serial
- output with embedded sync information
- Latency: As low as a few microseconds
- FPGA: Xilinx Kintex Ultrascale, KU040, KU060
Benefits
- Fully standards compliant - tested with ITU-T & other industry standard test suites.
- Robust error handling & resilience
- Processes metadata related to closed captions, AFD, timing & HDR
- Seamless switching between streams encoded with different settings including different resolutions, chroma formats and bit depths.
- Ultra-low latency
- Extensive options to customize the source code via use of parameters
- Single chip solution with no processor requirement
- Optimized resource utilization
- Easy to integrate
Deliverables
- Source Code or Netlist
- Simulation Model
- Hardware Test Platform
- Build Scripts
- Test Reports
- User Manual
- Design Documentation
- Constraint Files
- Test Benches
- Support for one year
Applications
- Broadcast
- Video Contribution & Distribution decoders
- Multi-format digital receivers (IRDs)
- Video / Play-out Servers
- High End Consumer Electronics
- Test & Measurement Equipment’s
- Aerospace & defense
- Medical
Block Diagram of the HEVC 4Kp60 Decoder, Supports 4:2:2, 10-bit decoding and 150Mbps bitrate
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