The H265-MP-D IP core implements a hardware video decoder for the High Efficiency Video Coding (HEVC) compression standard. The core complies with the Monochrome, Main, Main 10, and optionally the Monochrome 12, Main 4:2:2-10, and Main 4:2:2 12 profiles of the standard (ITU-T H.265 | ISO/IEC 23008-2).
The video decoder is designed for straightforward, trouble-free SoC integration. It operates on a stand-alone basis such that decoding proceeds without any assistance or input from the host processor. The core features streaming-capable AMBA® AXI-S interfaces for the stream and decoded pixel data. A standard AXI4-lite system bus interface gives the host real-time control and status access. An AXI4 memory interface for reading the incoming compressed video and storing the resulting decompressed video is independent of memory type—supporting SRAM, SDRAM, or DDRAM—and tolerant to the large delays and latencies typically present on a shared bus architecture.
The H265-MP-D is a custom hardware accelerator and uses local memories that maximize data reuse and minimize external memory bandwidth, so its power consumption and clock frequency requirements are much lower than any software, or hybrid software/hardware decoder implementation.
The H265-MP-D is a microcode-free design developed for reuse in ASIC and FPGA implementations. The design is scan-ready using strictly synchronous with positive-edge clocking and no internal tri-states. The core has been rigorously verified using Fraunhofer’s reference streams and is FPGA proven.