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HEVC/H.265 Main10 Profile Decoder IP for UHD(4K)
The Chips&Media WAVE410 is one of the most advanced hardware video decoder IP core, which supports the next generation HEVC(High Efficiency Video Coding) standard, also known as H.265.
The WAVE410 is fueled by advanced multicore architecture to deliver outstanding performance and scalability. The single core requires only about 100MHz clock frequencies to decode 1080p video at 30 frames per scond and it can be easily extent to 8K resolution at 60 frames per second.
In addition to its superior 4K decoding capabilities, the WAVE410 also provides the maximum bandwidth efficiency and exceptional power consumption required by today’ s most demanding across all connected devices.The WAVE410 includes CFrameTM technology, which achieves 50~70% of the significant bandwidth reduction, via efficient frame buffer management.
The WAVE410 video decoder IP core is suitable for application across all industry segment including ultra high-definition televisions(UHDTVs), set-top boxes(STBs),Smartphones, Tablet and other applications with support super high resolution.
The WAVE410 is fueled by advanced multicore architecture to deliver outstanding performance and scalability. The single core requires only about 100MHz clock frequencies to decode 1080p video at 30 frames per scond and it can be easily extent to 8K resolution at 60 frames per second.
In addition to its superior 4K decoding capabilities, the WAVE410 also provides the maximum bandwidth efficiency and exceptional power consumption required by today’ s most demanding across all connected devices.The WAVE410 includes CFrameTM technology, which achieves 50~70% of the significant bandwidth reduction, via efficient frame buffer management.
The WAVE410 video decoder IP core is suitable for application across all industry segment including ultra high-definition televisions(UHDTVs), set-top boxes(STBs),Smartphones, Tablet and other applications with support super high resolution.
Features
- Supported standards for Decoder
- ISO/IEC23008-2 HEVC , ITU-T Rec. H.265 Main Profile L5.0/L5.1
- Performancce
- Single Core
- 1920x1080p 30fps < 100MHz
- 3840x2160p 30fps < 300MHz(typical)*
- Dual Core
- 3840x2160p 60fps < 400MHz*
- Decoding Tools
- Fully Compatible with ISO/IEC 23008-2 HEVC(H.265) specification in Main profile10 High-tier
- Supports up to 8192x8192 pixel resolution(8Kx4K)
- I/P/B Picture Decoding
- Coding Unit(CU) sizes from 8x8 to 64x64
- Prediction Unit(PU) sizes from 4x4 to 64x64
- Transform Unit(TU) sizes from 4x4 to 32x32
- Supports all Intra Prediction sizes and modes
- Supports all Intra Prediction sizes and modes
- Advanced Motion Vector Prediction
- CABAC(Context Adaptive Binary Arithmetic Coding)
- De-blocking filter
- Sample Adaptive Offset(SAO) filter
- Tiles and WPP for multi-core extension
- Interface
- AMBA 32-bit APB interface for Host CPU
- AMBA 128-bit AXI interface for the external memory
Benefits
- HEVC/H.265 Hardware Decoder IP
- Supports HEVC Main10 Profile
- Brings 50 percent bandwidth savings compared to H.264/AVC
- Ideal Solution for UltraHD Devices
- Enables UltraHD(4Kx2K) videointo the home and even on hands
- Maximizes memory bandwith Efficiency by using its CFrameTM technology
- Scalable Multi-core Architecture
- Allows easy to deploy with Scalable and Flexible architecture
- Extensible up to 8K 60p
Deliverables
- Fully verified synthesizable RTL source code
- RTL test bench
- S/W User Guide
- Datasheet/Integration Guide
- Verification Guide
- Evaluation platform
Applications
- Smartphones
- Media Tablet PCs
- Portable Multimedia Players
- Desktop & Laptop PCs
- Digital TVs
- Digital Set-top boxes(STBs)
- Video Game Consoles
- Blu-ray Players
- Automotive Infotainment
Block Diagram of the HEVC/H.265 Main10 Profile Decoder IP for UHD(4K)
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WAVE
- MIPS proAptiv Superscalar Multiprocessor
- General purpose microprocessor incorporating a high performance L1 cache controller and virtual memory management support for high performance embedded system applications
- MCU with integrated 64-bit SRAM controller, Memory Protection Unit and real-time, low latency execution unit, optimized for low cost, low power microcontroller and embedded applications
- MPU incorporating a high performance instruction/data L1 cache controller and Memory Management Unit (MMU)
- Multiprocessor
- I-Class I6500 Multiprocessor