USB 3.1 PHY (10G/5G) in Samsung (14nm, 10nm, 11nm, 8nm, 5nm)
High accuracy sigma-delta digital-to-analog converter
The semi-digital FIR filter topology of the FIRDAC makes the FIRDAC behave as a multi-bit DAC. This gives the converter its excellent OOBN and makes the system robust against clock jitter and other error sources typically associated with 1-bit converters while maintaining excellent THD and good matching properties.
The AXIOM_FIRDAC is ideally suited for digital-to-analog conversion in front of (analog) class-D or class-AB amplifiers. Additionally this IP can be delivered together with up-sampling and interpolation filters as signal pre-processing. The design and layout of the FIRDAC is a highly automated process, easy to scale and good portable to several CMOS technologies.
The specifications and measurement results are based on a silicon implementation of the IP. Specifications can be modified to meet customer requirements. Porting to several technologies is possible in a contract development project.
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Block Diagram of the High accuracy sigma-delta digital-to-analog converter IP Core
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