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High Bandwidth In-Order RISC-V IP Core
Features
- 64-bit Core
- Ready for the most demanding workloads, Avispado supports large memory capacities with its 64-bit native data path.
- With its complete MMU support, Avispado is also Linux-ready, including multiprocessing.
- Vector Ready (optional VPU 823 - RISC-V vector unit)
- Avispado supports the upcoming RISC-V Vector Specification 1.0 as well as Semidynamics Open Vector Interface, giving you freedom of choice between your own custom vector unit and using Semidynamics offerings.
- Vector Instructions densely encode lots of computations, thereby reducing energy per operation.
- Vector Gather instructions support sparse tensor weights efficiently, helping machine learning workloads.
- Multiprocessor Ready
- Avispado supports cache-coherent Multiprocessing environments. Its native CHI interface can be tailored down to ACE or AXI, depending on your needs.
- Be it 2, 4, or hundreds of cores, Avispado is ready for your next SOC.
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RISC-V IP
- RISC-V processor - 32 bit, 5-stage pipeline
- 64-bit RISC-V application processor core with 7-stage pipeline
- Compact RISC-V Processor - 32 bit, 3-stage pipeline, 32 registers
- 64-bit RISC-V application processor core with L2 cache coherence
- Compact RISC-V Processor - 32 bit, 3-stage pipeline, 16 registers
- Dual-issue, 64-bit RISC-V application processor core with 7-stage pipeline