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High Data Rate Demodulator IP Core
The High Data Rate Demodulator IP core can demodulate BPSK, QPSK, offset-QPSK (OQPSK), 8PSK and 16QAM modulation schemes, all to a high performance level and at high symbol rates. The demodulator is highly flexible, supporting continuously variable software-selectable symbol rates of between 4.9kbaud and 40Mbaud, when operating with a fixed 100MHz system/ADC clock rate.
Features
- Versatile digital demodulation engine supporting BPSK, QPSK, offset-QPSK (OQPSK), 8PSK, 8QAM* (three variants), 16QAM, 32/64QAM (HDRM-D2 core only) & 16/32APSK (HDRM-D2 core only)
- Close to theoretical performance
- Option to increase datapath resolution to help cope with elevated levels of adjacent carrier interference (HDRM-D2 core only)
- N-stage symbol rate blind adaptive equaliser option reduces linear channel distortions such as multipath (HDRM-D2 core only)
- Supports continuously variable symbol rates
- Internal filter decimates up to a factor of 4096
- Supports typical rates of 4.9kbaud to 40Mbaud with 100MHz clock (range scales linearly with clock)
- Four matched filter configurations with alphas of 20%, 25%, 35% & 40% (others available on request)
- Fast acquisition algorithm
- Combined coarse/fine frequency scan
- High probability of first pass acquisition
- Highly configurable and versatile - fully programmable via simple microprocessor interface (SMPI)
- Fully programmable dynamic operation
- Independent acquisition & track parameters
- Configurable timing & carrier lock characteristics
- 10 to 14-bit I & Q datapath/ADC interface resolution*
- Constellation output interface suitable for connecting to soft-decision forward error correction (FEC)
- AGC control interface to analogue front-end
- Status interface reports real-time demodulation state
- Comes with software driver in C
- Extensive support for software monitoring
- Suitable for FPGA or ASIC implementation
- Synchronous design with single clock
- Hardware evaluation board (available extra)
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