High Data Rate Enhanced Demodulator IP Core

Features

• Versatile digital demodulation engine supporting BPSK, QPSK, offset-QPSK (OQPSK), 8PSK, 8QAM* (three variants), 16QAM, 32/64QAM (HDRM-D2 core only) & 16/32APSK (HDRM-D2 core only)
• Close to theoretical performance
• Option to increase datapath resolution to help cope with elevated levels of adjacent carrier interference (HDRM-D2 core only)
• N-stage symbol rate blind adaptive equaliser option reduces linear channel distortions such as multipath (HDRM-D2 core only)
• Supports continuously variable symbol rates
• Internal filter decimates up to a factor of 4096
• Supports typical rates of 4.9kbaud to 40Mbaud with 100MHz clock (range scales linearly with clock)
• Four matched filter configurations with alphas of 20%, 25%, 35% & 40% (others available on request)
• Fast acquisition algorithm
• Combined coarse/fine frequency scan
• High probability of first pass acquisition
• Highly configurable and versatile - fully programmable via simple microprocessor interface (SMPI)
• Fully programmable dynamic operation
• Independent acquisition & track parameters
• Configurable timing & carrier lock characteristics
• 10 to 14-bit I & Q datapath/ADC interface resolution*
• Constellation output interface suitable for connecting to soft-decision forward error correction (FEC)
• AGC control interface to analogue front-end
• Status interface reports real-time demodulation state
• Comes with software driver in C
• Extensive support for software monitoring
• Suitable for FPGA or ASIC implementation
• Synchronous design with single clock
• Hardware evaluation board (available extra)

• see the entire High Data Rate Enhanced Demodulator datasheet
• get in contact with High Data Rate Enhanced Demodulator Supplier