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High Density Single Port Reg File Compiler - Silterra 130 nm CL130G
ARM offers an array of silicon proven SRAM, Register File and ROM memory compilers for all types of SoC designs ranging from performance critical to cost sensitive and low power applications. As part of the ARM Processor / Graphics Optimized packages, ARM Fast Cache Instances deliver tuned performance, power and area when building ARM Processors, Graphics and System IP.
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Embedded Memory IP IP
- The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.
- UFS IP for high-performance, low-power interface targeting embedded or removable non-volatile mass storage memory devices
- UMC 0.11um Embedded High Voltage Mask Reduction AL Process standard synchronous high density single port SRAM memory compiler.
- UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler.
- UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler with redundancy.
- Embedded synchronous single port SRAM/ROM memory controller with AXI slave port.