English
Switching regulator, inductor-based, PWM mode, high efficiency, DELTA standard
You are here:
High Density Two Port Reg File Compiler - Samsung 65 nm CMOS10LP
ARM offers an array of silicon proven SRAM, Register File and ROM memory compilers for all types of SoC designs ranging from performance critical to cost sensitive and low power applications. As part of the ARM Processor / Graphics Optimized packages, ARM Fast Cache Instances deliver tuned performance, power and area when building ARM Processors, Graphics and System IP.
View High Density Two Port Reg File Compiler - Samsung 65 nm CMOS10LP full description to...
- see the entire High Density Two Port Reg File Compiler - Samsung 65 nm CMOS10LP datasheet
- get in contact with High Density Two Port Reg File Compiler - Samsung 65 nm CMOS10LP Supplier
Embedded Memory IP IP
- The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.
- UFS IP for high-performance, low-power interface targeting embedded or removable non-volatile mass storage memory devices
- UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler.
- UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler with row redundancy.
- UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler.
- Memory Controller for embeded systems supporting SDRAM and NandFlash, with bootstrap loader