English
You are here:
High Density Two Port Reg File Compiler - TSMC 65 nm CLN65LP
ARM offers an array of silicon proven SRAM, Register File and ROM memory compilers for all types of SoC designs ranging from performance critical to cost sensitive and low power applications. As part of the ARM Processor / Graphics Optimized packages, ARM Fast Cache Instances deliver tuned performance, power and area when building ARM Processors, Graphics and System IP.
View High Density Two Port Reg File Compiler - TSMC 65 nm CLN65LP full description to...
- see the entire High Density Two Port Reg File Compiler - TSMC 65 nm CLN65LP datasheet
- get in contact with High Density Two Port Reg File Compiler - TSMC 65 nm CLN65LP Supplier
Embedded Memory IP IP
- The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.
- UFS IP for high-performance, low-power interface targeting embedded or removable non-volatile mass storage memory devices
- UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler.
- UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler with redundancy.
- Fast Access Controller – a plug-and-play IP solution for fast embedded Flash Programming and Memory Testing
- Memory Controller for embeded systems supporting SDRAM and NandFlash, with bootstrap loader