High Density Via Programmable ROM Compiler - Samsung 65 nm CMOS10LP
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Embedded Memory IP IP
- The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.
- UFS IP for high-performance, low-power interface targeting embedded or removable non-volatile mass storage memory devices
- Ethernet MAC IP, 10/100/1G Ethernet MAC, DMA (Direct Memory Access) function embedded, Soft IP
- UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler.
- Dual Port, Low Voltage, GF 55LPx with Embedded Flash, HVt & SVt, SRAM Memory Compiler
- Memory Controller for embeded systems supporting SDRAM and NandFlash, with bootstrap loader