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High Density Via Programmable ROM Compiler - TSMC 28 nm CLN28HPC
ARM offers an array of silicon proven SRAM, Register File and ROM memory compilers for all types of SoC designs ranging from performance critical to cost sensitive and low power applications. As part of the ARM Processor / Graphics Optimized packages, ARM Fast Cache Instances deliver tuned performance, power and area when building ARM Processors, Graphics and System IP.
Features
- High density and low power architecture
- Multiple power management modes with power gating and multi-voltage operation
- Flexible margining features
- Optional integrated pipeline
- Soft Error repair
- Advanced test features
- Pseudo Scan
Benefits
- Minimizes die area to reduce die and packaging cost
- Flexible power management allows packaging cost reduction, competitive product with higher battery life
- Allows yield/performance tradeoff
- Allows high throughput
- Enables yield optimization
- Enhances product quality and minimizes field returns
- Cuts down test time drastically by orders of magnitude reducing overall product test cost significantly
- Improved product quality lowers field failures
Deliverables
- Front End (FE) and Back End (FB) views with full suite of design views and models that support most of the industry's popular design tools can be downloaded from the ARM DesignStart web site at: http://www.arm.com/support/designstart.php
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Embedded Memory IP
- The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.
- General purpose microprocessor incorporating a high performance L1 cache controller and virtual memory management support for high performance embedded system applications
- MCU with integrated 64-bit SRAM controller, Memory Protection Unit and real-time, low latency execution unit, optimized for low cost, low power microcontroller and embedded applications
- High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for TSMC 28HPM
- 32-bit OTP anti-fuse memory IP with embedded redundancy mechanism and margin check
- UMC 0.45um Logic process standard gate array asynchronous embedded array high density two port (1R1W) SRAM memory compiler.