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High-performance, compact, low-power 32-bit cores for MCU and real-time embedded applications
The MIPS32 M4K/4K family of cores from Wave Computing are high performance, low-power, 32-bit MIPS RISC cores designed for custom system-on-silicon applications. They are ideally positioned to support new products for emerging segments of the routing, network access, network storage, residential gateway, and smart mobile device markets. The cores are especially well-suited for microcontroller and hardware accelerator applications, as well as systems requiring multiple cores, when high performance density is critical.
Features
- Based on the well-proven MIPS Release 2 architecture, the cores are designed around a 5-stage pipeline, SRAM interface and comprehensive debug features.
- Include the MIPS16e Application Specific Extension (ASE), reducing code size by up to 40%.
- Delivers a performance of 1.6 DMIPS/MHz and 3.4 Coremarks/MHz.
- Memory Management Unit (MMU) consists of a simple, Fixed Mapping Translation (FMT) mechanism for applications that do not require the full capabilities of a Translation Lookaside Buffer (TLB) based MMU.
- Include two different Multiply/Divide Unit (MDU) implementations, selectable at build-time, allowing the implementor to trade off performance and area.
- High-performance MDU option implements single cycle 32x16-bit MAC instructions or two cycle 32x32-bit, which enable DSP algorithms to be performed efficiently.
- Area-efficient MDU option handles multiplies with a one-bit-per-clock iterative algorithm.
- Cacheless - in lieu of caches, includes a simple interface to SRAM-style devices. This interface may be configured for independent instruction and data devices or combined into a unified interface.
- SRAM interface allows deterministic response, while still maintaining high performance.
- Optional Enhanced JTAG (EJTAG) block allows for single-stepping of the processor as well as instruction and data virtual address/value breakpoints.
- Real-time tracing of instruction program counter, data address, and data values can be supported.
- MIPS32-Compatible Instruction Set
- MIPS32 Enhanced Architecture (Release 2)
- MIPS16e Code Compression: 16 bit encodings of 32 bit instructions to improve code density
- Memory Management Unit: Simple Fixed Mapping Translation (FMT) mechanism
- Simple SRAM-Style Interface: Cacheless operation enables deterministic response and reduces size
- CorExtend User Defined Instruction Set Extensions: Allows user to define and add instructions to the core at build time
- Multi-Core Support: External lock indication enables multi-processor semaphores based on LL/SC instructions
- Multiply/Divide Unit (high-performance configuration): Maximum issue rate of one 32x16 multiply per clock
- Multiply/Divide Unit (area-efficient configuration): 32 clock latency on multiply
- Coprocessor 2 interface: 32 bit interface to an external coprocessor
- Power Control: Minimum frequency: 0 MHz
- EJTAG Debug and MIPS Trace
- Testability: Full scan design achieves test coverage in excess of 99% (dependent on library and configuration options)
Benefits
- Designed for semiconductor manufacturing companies, ASIC developers, and system OEMs who want to rapidly integrate their own custom logic and peripherals with a high-performance RISC processor.
- Highly portable across processes, and can be easily integrated into full system-on-silicon designs, allowing developers to focus their attention on end-user products.
- Provide highly performance-efficient, feature-rich solutions for a broad range of real-time, cost-sensitive embedded system applications.
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