This memory controller supports DDR2/3 SDRAM. DDR2/3 memory controller is a high-speed interface used for data read/write between internal engine and outside SDRAM bus, and transfers the internal signal to meet the SDRAM specification. The DDR2/3 memory controller includes several Sub- Arbiters and a MEM_CORE module. The MEM_CORE module includes a Main-Arbiter module and a DDR controller module. Sub-Arbiter supports 4 masters. Sub-Arbiter would be placed in partition or in memory controller. Main- Arbiter supports 16 masters. The memory arbiter will do arbitration one all the masters’ (internal engines) request and send those request to DDR controller. The DDR controller will convert the internal request to DRAM chip protocol for data read/write. The DDR controller also implements the DRAM refresh, DRAM
dynamic power down, DRAM Scramble and DRAM Private Usage functions.