Mobiveil's DDR4/3 Memory Controller is a highly flexible and configurable design targeted for high performance enterprise server and real-time consumer applications that utilize computational elements like graphics controllers, general purpose, digital signal processors, etc. The controller architecture is carefully tailored to achieve reliable high-frequency operation, dynamic power management, error injection and support for rapid system debug.
DDR4/3 Controller is part of Mobiveil’s Storage and Memory controller family of IP solutions which also includes LPDDR2/3, UNEX, IFC, and eSDHC IP cores.
The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. Mobiveil solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible AXI System interface makes it easy to be integrated into wide range of applications. Mobiveil solution provides highly scalable bandwidth through configurable lanes, widths and frequencies.
DDR4/3 controller leverages Mobiveil’s years of experience in HyperTransport, PCI, PCIe and RapidIO technologies and the expertise in creating system validated IP solutions with RTL, synthesis, simulation, board and software elements to offer lowest risk in terms of compliance and inter operability.
- Compliant with AXI4 (AMBA AXI Protocol Version: 2.0)
- Compliant with DFI 3.0 Specification
- Compliant with JEDEC DDR3, DDR3L and DDR4 standards
- Supports 64, 32, 16 and 8 bit Memory SDRAM for DDR3L and DDR4
- Data/Address Interface supports 64-byte and 32-byte wrapping, Up to 256 byte transactions (16 AXI beats)
- Chip select interleaving support
- Support for double bit error detection and single bit error correction ECC or accumulated ECC for 8-bit, 16-bit, and 32-bit interfaces
- Support for error injection
- Superior architecture-optimized for high performance, low power and low gate count
- Feature rich, highly flexible, scalable, configurable and timing friendly design
- Ease of integration
- Verified with leading VIP
- Configurable RTL Code
- HDL based test bench and behavioral models
- Test cases
- Protocol checkers, bus watchers and performance monitors
- Configurable synthesis shell
Block Diagram of the High Performance DDR4/3 Memory Controller IP Core