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High performance DSP core with VLIW/SIMD/decoupled architectures
NeuroMatrix® Core 3 (NMC3) is а high performance DSP core with VLIW/SIMD/decoupled architectures. The core includes a 32-bit RISC processor and a 64-bit VECTOR co-processor to support vector operations with elements of variable bit length. The NMC3 core has been silicon proven. It has scalable performance and original instruction set.
Features
- 32/64-bit RISC Core
- 3 scalar instructions per clock cycle (ALU operation, address modification and memory read/write operation)
- 64-bit Vector Coprocessor (fixed point):
- Programmable data length from 2 to 64 bits packed to 64 bit data words
- Basic operation is matrix by matrix multiplication
- Two saturation operations execution per clock cycle
- Performance (MAC - Multiplication and Accumulation per clock cycle) -
- 2 MAC for 32-bit data
- 4 MAC for 16-bit data
- 24 MAC for 8-bit data
- 80 MAC for 4-bit data
- 224 MAC for 2-bit data
- 1K*64 bit Instruction Cache
- Up to 4 External Address Generators
- Up to 4 Internal Memory Banks Support
- AXI 3.0 External Memory Interface
- Up to 32 External/internal Interrupts Support
- Two 32-bit Timers
- DMA controller
Applications
- Hydro- and radiolocation
- IR and video processing
- Artificial Neural net emulation
- Navigation
- CDMA и TDMA base stations
- Vector and matrix computations
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