Perceptia’s DeepSub™ pPLL08F is a family of high performance RF frequency synthesizer PLLs featuring industry leading jitter (sub-300fs), phase noise and compact area suitable for RF applications, including 5G and WiFi at frequencies up to 8GHz. It is suitable for use as an LO and/or clocking ADCs/DACs with demanding SNR requirements.
Perceptia’s second generation pPLL08F family is available on technologies from 5nm to 40nm and across multiple foundry partners. We are continually expanding the range of technologies where it is silicon proven and can quickly port it to other technologies or foundries upon request.
pPLL08 uses a LC tank DCO to achieve the performance demands of critical RF systems. It is low power (< 3 mW in GF 22FDX) and is extremely compact (< 0.05 sq mm). The all digital architecture minimises interference from other circuits on the same die, making it capable of supporting SNDR better than 60dB.
pPLL08 integrates easily into any SoC design and includes all the views and models required by back end flows.
The pPLL08F is built using Perceptia’s second generation all digital PLL technology. This robust technology delivers identical performance across many processes, regardless of PVT conditions. It consumes a fraction of the area of an analog PLL whilst maintaining comparable performance.
pPLL08F can be used as an integer-N PLL or as a fractional-N PLL. The fractional-N mode provides a high flexibility to choose the best combination of input and output clock frequencies at the system level.
Perceptia further provides integration support and offers customization and migration services.