Two clock cycle machine cycle implementation of the Z80/Z180 instruction set. Optimized for ASIC or FPGA implementations.
This machine structure is derived from that used in the Rabbit
Semiconductor microprocessors. Performance for those
designs (which are more complex) is 200MHz in 90nm, or
- Full Z80/Z180 instruction set. Separate memory and I/O buses,
- optimized for direct connection to standard ASIC or FPGA
- memories and industry-standard peripheral functions. Separate
- interrupt vector bus for use with an optionaql external interrupt
- Optional full test suite.
- Optional full internal design documentation.
- Full Z80/Z180 code compatibility.
- Average 33% clock cycle performance improvement over the
- standard Z180 timing. Average 50% clock cycle performance
- improvement over the standard Z80 timing.
- Uniform machine cycle timing makes interface design simple.
- Dedicated buses also simplify interface design.
- Verilog source code.
- Optional test suite.
- Optional internal design documentation.