This FFT is an efficient implementation of the Decimation in Frequency (DIF) Cooley-Tukey FFT. Using low FPGA/ASIC resources and a high clock speed, this design manages high throughput by careful design optimization. This results in an IP core well balanced between logic and throughput.
The FFT IP consists of two separate variants:
A complex valued IFFT/FFT.
A real valued IFFT/FFT.
The real valued FFT uses a half size transform and a combining pass to generate the full transform. This means that the core has only half the scratch memory and cycle count of the complex valued transform.
- Real or Complex valued IFFT/FFT options
- Per transform selection of FFT size from 8 to 32768 points
- Per transform selection of FFT or IFFT
- Efficient mixed radix 4/2 dragonfly for low cycle count
- Block floating point scaling ensures excellent dynamic range
- Data and twiddle bit widths are parameterized
- IEEE-754 convergent rounding after twiddle multiplications
- 1/8 twiddle table storage for lowest ROM requirements
- Choice of interfacing options
- Synthesis scripts
- MATLAB and C++ bit exact model
- OFDM system such as :