This FFT is an efficient implementation of the Decimation in Frequency (DIF) Cooley-Tukey FFT. Using low FPGA/ASIC resources and a high clock speed, this design manages high throughput by careful design optimization. This results in an IP core well balanced between logic and throughput.
The FFT IP consists of two separate variants:
A complex valued IFFT/FFT.
A real valued IFFT/FFT.
The real valued FFT uses a half size transform and a combining pass to generate the full transform. This means that the core has only half the scratch memory and cycle count of the complex valued transform.