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MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane
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High-Performance Low-Power 32-bit RISC core
The C310 is a member of theC*Core TM High-Performance Low-Power 32-bit RISC core family. It has been designed for high-performance and cost-sensitive embedded applications, with particular emphasis on reduced system power consumption, making it suitable for battery-operated, portable products. The C310 extends the C210 instruction set and functionality by integrating an integer array multiplier, branch prediction and folding, improved pipelining of load and store operations, and a deeper instruction buffer to improve memory bandwidth utilization.
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