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Process Detector (For DVFS and monitoring process variation), TSMC N3
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High-Performance Single Data Rate SDRAM Controller
Description: CORESDR provides a high performance interface to single data rate(SDR) synchronous dynamic random access memory(SDRAM) devices. CORESDR accepts read and write commands using the simple local bus interface, and translates these requests to the command sequences required by SDRAM devices. CORESDR also performs all initialization and refresh functions. CORESDR uses bank management techniques to monitor the status of each SDRAM bank. Banks are only opened or closed when necessary, minimizing access delays. Up to four banks can be managed at one time.
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SDRAM Controller IP
- High Performance DDR4/3 Memory Controller
- 32/64-bit PC133 SDRAM Controller
- LPDDR4 Controller Core
- Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process.
- DDR3 SDRAM Controller supporting Altmemphy
- DDR SDRAM Controller supporting Altmemphy