CoreSDR_AHB provides a high performance interface to single data rate(SDR) synchronous dynamic random access memory(SDRAM) devices. CoreSDR_AHB accepts read and write commands using the AHB bus slave interface, and translates these requests to the command sequences required by SDRAM devices. CoreSDR_AHB also performs all initialization and refresh functions. CoreSDR_AHB uses bank management techniques to monitor the status of each SDRAM bank. Banks are only opened or closed when necessary, minimizing access delays. Up to four banks can be managed at one time.
- High performance, single data rate controller for standard SDRAM chips and dual in-line memory modules (DIMMs)
- Synchronous interface, fully pipelined internal architecture
- Supports up to 1,024 MB of memory
- Bank management logic monitors status of up to 8 SDRAM banks
- Support for AHB bus slave interface
- Data access of 8, 16, or 32 bits are allowed by masters