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High-speed 9-bit, 1.2GSps ADC in 40nm CMOS
This high-speed Analog to Digital Converter (ADC) IP block is implemented in 40nm CMOS process, with fully differential signal path and 12 interleaved outputs specifically designed for wideband signal handling.
The 9-bit ADC is based on 12 timing interleaved 9-bit SAR ADCs, each running at a maximum conversion speed of 100MSps. The typical ADC SFDR is 57dB for a 50MHz input signal with 50dB of SNR. Minimum simulated ENOB is 8.1 LSB. The monolithic ADC is designed to operate with a single external supply, ranging from 1.6V to 3.3V.
The 9-bit ADC is based on 12 timing interleaved 9-bit SAR ADCs, each running at a maximum conversion speed of 100MSps. The typical ADC SFDR is 57dB for a 50MHz input signal with 50dB of SNR. Minimum simulated ENOB is 8.1 LSB. The monolithic ADC is designed to operate with a single external supply, ranging from 1.6V to 3.3V.
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