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High-speed 9-bit, 1.2GSps ADC in 40nm CMOS
This high-speed Analog to Digital Converter (ADC) IP block is implemented in 40nm CMOS process, with fully differential signal path and 12 interleaved outputs specifically designed for wideband signal handling.
The 9-bit ADC is based on 12 timing interleaved 9-bit SAR ADCs, each running at a maximum conversion speed of 100MSps. The typical ADC SFDR is 57dB for a 50MHz input signal with 50dB of SNR. Minimum simulated ENOB is 8.1 LSB. The monolithic ADC is designed to operate with a single external supply, ranging from 1.6V to 3.3V.
The 9-bit ADC is based on 12 timing interleaved 9-bit SAR ADCs, each running at a maximum conversion speed of 100MSps. The typical ADC SFDR is 57dB for a 50MHz input signal with 50dB of SNR. Minimum simulated ENOB is 8.1 LSB. The monolithic ADC is designed to operate with a single external supply, ranging from 1.6V to 3.3V.
Features
- Differential, 9-bit, 1.2GSps interleaving SAR ADC
- Optimized for 10ps signal delay variation over 10°C
- Built in LDOs and reference buffers with >29dB PSRR across all frequencies
- Built-in sleep mode
- Wide temperature operation (-40°C to 115°C)
- 1.6V to 3.3V supply operation
- TSMC 40nm CMOS (1P7M)
- Silicon proven
Benefits
- Wideband signal handling
- 10ps signal delay variation
Deliverables
- Design deliverables:
- GDSII
- Schematics and layouts of the IP sub-blocks
- Verilog-A model of the IP sub-blocks
- Simulation states and full suite of test benches in Cadence
- Documentation:
- Datasheet
- Design documents including block level documentation
Applications
- Crystal drivers
- Timing applications
- Digital wideband signal processing
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