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UFS 3.0 Host Controller with AES Encryption compatible with M-PHY 4.0 and UniPro 1.8
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High-Speed AES Encryption Cores
D’Crypt’s AES core is a high-performance pipelined implementation of the AES (Rijndael) encryption algorithm. Optimized for PLD architectures, the core achieves in excess of 2.5Gbit/s encryption and decryption throughput on 128-bit blocksizes when implemented on Altera APEX 20KE or equivalent devices. It employs a 128-bit key and features zero key-setup latency on both encryption and decryption. With key-agility and selective bypass control, D’Crypt’s AES core is the ideal building block for high-performance packet-smart routers and switches.
Features
- >2.5 Gbits per second (Gbps) throughput for fiber-speed encryption
- Key-agility on both encryption and decryption allows keys to be switched without stalling the core
- Simple streaming architecture obviates the need for elaborate control logic outside the core
- Bypass control allows data flow-through for selective encryption
- Simple 32-bit data and key ports reduce logic required to interface to high-speed standards
Block Diagram of the High-Speed AES Encryption Cores IP Core
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