High Speed and Density Diffusion Prog ROM Compiler - 1st Silicon 180 nm FSI018
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Embedded Memory IP IP
- The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.
- UFS IP for high-performance, low-power interface targeting embedded or removable non-volatile mass storage memory devices
- UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler.
- UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler with row redundancy.
- Embedded synchronous single port SRAM/ROM memory controller with AXI slave port.
- FAB1 0.18um 1.8V/5V Embedded Memory Flash Ultra LL Process miniLib+_x000D_