English
You are here:
High Speed and Density Diffusion Prog ROM Compiler - 1st Silicon 180 nm FSI018
ARM offers an array of silicon proven SRAM, Register File and ROM memory compilers for all types of SoC designs ranging from performance critical to cost sensitive and low power applications. As part of the ARM Processor / Graphics Optimized packages, ARM Fast Cache Instances deliver tuned performance, power and area when building ARM Processors, Graphics and System IP.
Features
- High density and low power architecture
- Multiple power management modes with power gating and multi-voltage operation
- Flexible margining features
- Optional integrated pipeline
- Soft Error repair
- Advanced test features
- Pseudo Scan
Benefits
- Minimizes die area to reduce die and packaging cost
- Flexible power management allows packaging cost reduction, competitive product with higher battery life
- Allows yield/performance tradeoff
- Allows high throughput
- Enables yield optimization
- Enhances product quality and minimizes field returns
- Cuts down test time drastically by orders of magnitude reducing overall product test cost significantly
- Improved product quality lowers field failures
Deliverables
- Front End (FE) and Back End (FB) views with full suite of design views and models that support most of the industry's popular design tools can be downloaded from the ARM DesignStart web site at: http://www.arm.com/support/designstart.php
View High Speed and Density Diffusion Prog ROM Compiler - 1st Silicon 180 nm FSI018 full description to...
- see the entire High Speed and Density Diffusion Prog ROM Compiler - 1st Silicon 180 nm FSI018 datasheet
- get in contact with High Speed and Density Diffusion Prog ROM Compiler - 1st Silicon 180 nm FSI018 Supplier
Embedded Memory IP IP
- The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.
- UFS IP for high-performance, low-power interface targeting embedded or removable non-volatile mass storage memory devices
- UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler.
- UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler with row redundancy.
- Embedded synchronous single port SRAM/ROM memory controller with AXI slave port.
- MCU with integrated 64-bit SRAM controller, Memory Protection Unit and real-time, low latency execution unit, optimized for low cost, low power microcontroller and embedded applications