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High Speed and Density Two Port Reg File Compiler - HHNEC 180 nm HNC018G
ARM offers an array of silicon proven SRAM, Register File and ROM memory compilers for all types of SoC designs ranging from performance critical to cost sensitive and low power applications. As part of the ARM Processor / Graphics Optimized packages, ARM Fast Cache Instances deliver tuned performance, power and area when building ARM Processors, Graphics and System IP.
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Embedded Memory IP IP
- The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.
- UFS IP for high-performance, low-power interface targeting embedded or removable non-volatile mass storage memory devices
- UMC 0.45um Logic process standard gate array asynchronous embedded array high density two port (1R1W) SRAM memory compiler.
- Embedded synchronous single port SRAM/ROM memory controller with AXI slave port.
- Memory Controller for embeded systems supporting SDRAM and NandFlash, with bootstrap loader
- MCU with integrated 64-bit SRAM controller, Memory Protection Unit and real-time, low latency execution unit, optimized for low cost, low power microcontroller and embedded applications