The High-Speed Digital PLL is intended for applications such the Clock-Multiplying-Unit in a SERDES or a Clock-Driver where the the output frequency is not an integer multiple of the reference frequency. The High-Speed Digital PLL has been realized in TSMC's 40G technology. It does not require off-chip components, is highly reconfigurable, has very good jitter performance. In addition, it is very high speed, can be programmed over a wide range (guaranteed 0.5-6.25 GHz output), is low in power (32 mW at 5GHz), requires only a minimal amount of area in an integrated circuit, and includes a high-performance output driver capable of driving off-chip into 50 ohms at full-speed. Since most of the high-speed circuitry is digital, it is also readily customizable and portable to other technologies.