English
You are here:
High Speed Dual Port SRAM Compiler - Samsung 65 nm CMOS10SF
ARM offers an array of silicon proven SRAM, Register File and ROM memory compilers for all types of SoC designs ranging from performance critical to cost sensitive and low power applications. As part of the ARM Processor / Graphics Optimized packages, ARM Fast Cache Instances deliver tuned performance, power and area when building ARM Processors, Graphics and System IP.
View High Speed Dual Port SRAM Compiler - Samsung 65 nm CMOS10SF full description to...
- see the entire High Speed Dual Port SRAM Compiler - Samsung 65 nm CMOS10SF datasheet
- get in contact with High Speed Dual Port SRAM Compiler - Samsung 65 nm CMOS10SF Supplier
Embedded Memory IP IP
- The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.
- UFS IP for high-performance, low-power interface targeting embedded or removable non-volatile mass storage memory devices
- UMC 0.45um Logic process standard gate array asynchronous embedded array high density two port (1R1W) SRAM memory compiler.
- UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler.
- UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler with row redundancy.
- UMC 0.11um Embedded High Voltage Mask Reduction AL Process standard synchronous high density single port SRAM memory compiler.