High-Speed LVDS (SERDES) Transceiver
Capable of data rates of up to 500 MBits/s per lane on basic FPGA devices and 1 Gbits/s+ on higher-end FPGAs.
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Block Diagram of the High-Speed LVDS (SERDES) Transceiver IP Core
![High-Speed LVDS (SERDES) Transceiver Block Diagam](http://www.design-reuse.com/sip/blockdiagram/27371/20150320113030-main-lvds_serdes_block_diag.png)