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High speed Receiver serial interface
CoreJESD204BRX is the receiver conforming to the JEDEC JESD204B standard. This specification describes a high speed serial interface for data converters. This IP core supports 2 default data rates, 1.25 Gbps and 2.5 Gbps per lane. This means 10Gbps can be achieved across the 4 lanes of the CoreJESD204BRx for most configurations. The Core can be reconfigured through the APB interface to allow EPCS mode to achieve a higher data rates.
Features
- Designed to JEDEC JESD204B specification
- Enables interfacing of JESD204B compliant DAC convertors with SmartFusion2
- Supports 1, 2, 4, or 8 lanes
- Supports Subclasses 0, 1 and 2
- Sync~ signal encoding
- Performs word alignment
- Performs 8B/10B decoding
- Recovers link configuration parameters
- Performs lane alignment buffering, monitoring and correction
- Performs user-enabled frame alignment, monitoring and correction
- Performs octet reconstruction
- Performs user-enabled descrambling
- Error detection
- Supports data width of 16, 32, or 64 bits
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