The LogiCORE™ IP UltraScale™ High Speed SelectIO Wizard generates customized HDL wrappers to configures the UltraScale FPGA on-chip SelectIO. The wizard’s customization GUI allows users to configure one bank with up to two interfaces of high-speed Select IO Interfaces using the Native mode components. The GUI will set up the Native mode components clocking and capture, primites. The capture methods and IO standards may be selected as well as pin planning.
- Up to two interfaces for RX, TX and RXTX Separate and one interface for RXTX Bidirectional with different configurations are supported
- Each interface provides RX, TX, RXTX Separate and RXTX Bidirectional bus configurations with up to 46 bits per bank for single-ended signaling and 23 bits per bank for differential signaling
- Serialization factor of four and eight are supported
- Dynamic Phase Alignment (DPA) mode for the RX data capture scheme
- Delay configuration for each interface
- Bank selection and I/O planning to generate valid constraints
- Use pin update in I/O planning to update the required connections among design blocks in RTL