Granite Semicom has just shipped GDS-II of its totally-integrated (no off-chip components) Clock-Driver and Clock-Multiplying-Unit IP block including fractional-N in TSMC’s 40LP process; silicon is expected Q2 2013. In addition to porting its TSMC 40G version, a number of minor changes were incorporated. The oscillator was improved to have higher speed and less jitter, for a given power. Some critical current sources were modified to give an expected 40% reduction in long-term accumulated jitter. In addition, some feedback dividers where changed to give lower power. This block is intended for applications such as the CMU in a SERDES PHY, and for clock-driver applications. This IP block is a digital phased-lock-loop, plus an integrated voltage and current reference, a variety of input amplifiers (single-ended and differential, dc and ac-coupled), a number of programmable dividers, a serial interface for programming, and a high-speed 50 ohm driver capable of driving off-chip at full-speed. The specification is for the Digital PLL (DPLL_40LP) to operate between 0.5GHz and 7.5GHz over process corners between -40 and +125 degrees celsius; the power dissipation is less than 30 mw (for a 5GHz output), and the IP requires a 0.11 mm^2 area (not including pads and the output driver). Long term accumulated jitter is specified at less than 1ps rms accumulated over 260 periods.
- Wide range and programmability (0.5GHz to 7.5GHz)
- Size (0.11mm^2)
- Power (< 30mW at 5Ghz)
- Jitter (< 1ps rms accummulated over 260 periods at 5Ghz)
- Fast Locking (< 10us with calibration, < 1us without calibration)
- Serial (SPI) or parallel interface included
- Fractional-N Division included
- Full-speed off-chip buffer included
- Highly-programmable input and output options
- Customization for "customer needs" available
- A "digital PLL" is almost a necessity in 40nm and below; analog PLLs have too many unpredictable issues.
- Verilog for system integration
Block Diagram of the High-Speed, Wide-Range Digital PLL in TSMC 40LP