High Throughput Elliptic Curve Cryptography hardware acceleration Core

Features

• Supports any EC over GF(p) of the simplified Weierstrass form that is commonly defined in ECC standards such as NIST, SEC2, Brainpool;
• Supported operations: EC Digital Signature Algorithm (ECDSA) Signature/Verification1 and EC Scalar Multiplication (ECSM)
• Supports any key size up to the maximum specified in the pre-synthesis stage;
• Configurable architecture for achieving the required performance / silicon area level;
• Resistant against both Simple and Statistical Timing side channel Attacks (STA), and Simple Power Analysis (SPA) attacks;
• APB interface for loading curve parameters and private key and unloading the result

Benefits

• Flexibility to trade die area for operations/seconds
• Suitable for FPGA targets by making use of hard DSP and RAM resources
• Higher operations per seconds . Example application; V2X communications.

Deliverables

• RTL
• Testbench
• Software libraries

Block Diagram of the High Throughput Elliptic Curve Cryptography hardware acceleration Core

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