This IP core is available in either normal or high throughput configurations. The normal configuration instances a single fully parallel stage, equivalent to 32 ACS units, decoding a single message bit per clock cycle. The high throughput version instances 2 fully parallel stages, equivalent to 64 ACS units, and an interleaved traceback memory architecture. This decoder produces 2 message bits per clock cycle, twice that of conventional Viterbi decoders.
The core can be used for streaming or packetised data applications. By using signed LLR input data it naturally supports de-puncturing by inserting zeros.
The traceback operates by performing a 64-bit block decode after a specified traceback length, and then moving forward a block length and repeating. In this way a high througput is maintained with low memory access requirements.
The traceback memory requirements are significantly lower than other Viterbi decoders, by implementing a novel architecture.