This IP core is available in either normal or high throughput configurations. The normal configuration instances a single fully parallel stage, equivalent to 32 ACS units, decoding a single message bit per clock cycle. The high throughput version instances 2 fully parallel stages, equivalent to 64 ACS units, and an interleaved traceback memory architecture. This decoder produces 2 message bits per clock cycle, twice that of conventional Viterbi decoders.
The core can be used for streaming or packetised data applications. By using signed LLR input data it naturally supports de-puncturing by inserting zeros.
The traceback operates by performing a 64-bit block decode after a specified traceback length, and then moving forward a block length and repeating. In this way a high througput is maintained with low memory access requirements.
The traceback memory requirements are significantly lower than other Viterbi decoders, by implementing a novel architecture. For FPGA a dual-port memory architecture is appropriate, whereas for ASIC single port memories are used.
- Constraint length 7. Generator polynomials g0 = 1338 g1 = 1718.
- Decoding 1 or 2 message bits per clock cycle.
- Block based traceback from best state.
- Optional trellis tail biting for packetised data.
- Optional trellis head pinning for packetised data.
- Low latency equal to 2.5x block length.
- Signed 6-bit soft decision (LLR) inputs for multilevel QAM decoding.
- De-puncturing support.
- Automatic normalization.
- Parameterisable soft core