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High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for GLOBALFOUNDRIES 40LP
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Highly-Configurable 32-bit Processor
The AndesCore N9 Family is intended for deeply embedded applications that require optimal interrupt response features, including wireless networking and sensors, micro-controllers, automotive electronics, and industrial control systems. The low-power N9 Family of processors features low gate count, low interrupt latency, and low-cost debug. The processor family provides superior performance and excellent interrupt handling response while meeting the challenges of low dynamic and static power constraints.
The AndesCore N9 Family of CPU cores implement v3, the AndeStar™ patented 32-bit RISC-style CPU architecture. The designer can configure certain parameters to adjust the CPU’s size, power, and performance. For example, the N9 core can be configured with 16 or 32 general registers, two or three read ports on the register file, one or two write ports, a fast or a small multiplier, a 24-bit or 32-bit address space, and different bus (APB, AHB, AHB-Lite, AXI) interfaces to connect to the rest of the system.
The AndesCore N9 Family of CPU cores implement v3, the AndeStar™ patented 32-bit RISC-style CPU architecture. The designer can configure certain parameters to adjust the CPU’s size, power, and performance. For example, the N9 core can be configured with 16 or 32 general registers, two or three read ports on the register file, one or two write ports, a fast or a small multiplier, a 24-bit or 32-bit address space, and different bus (APB, AHB, AHB-Lite, AXI) interfaces to connect to the rest of the system.
Features
- High performance V3 ISA on a compact CPU architecture
- Superior total performance deliverable
- Efficient pipeline optimized for Local Memory accesses
- High configurability including AXI bus support
Benefits
- Performance
- Highly compact program size through AndeStar™ V3 ISA
- Static branch predication to speed up loop control
- Low latency vectored interrupt
- Optional saturation instructions for efficient voice applications
- Processor state bus to simplify SoC design and debugging
- Flexibility
- All-C Embedded Programming
- Stack protection hardware to help determining stack size needed,
- and detect runtime overflow error
- Support boot-up from Instruction Local Memory
- Power management
- Low power modes initiated by SW or SoC
- PowerBrake technology to reduce peak power consumption
Applications
- Wireless device
- Wireless charger
- Touch screen controller
- Storage device
- Industrial control
- Biometrics device
- GPS
- Game console
Block Diagram of the Highly-Configurable 32-bit Processor IP Core
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