The AndesCore N9 Family is intended for deeply embedded applications that require optimal interrupt response features, including wireless networking and sensors, micro-controllers, automotive electronics, and industrial control systems. The low-power N9 Family of processors features low gate count, low interrupt latency, and low-cost debug. The processor family provides superior performance and excellent interrupt handling response while meeting the challenges of low dynamic and static power constraints.
The AndesCore N9 Family of CPU cores implement v3, the AndeStar™ patented 32-bit RISC-style CPU architecture. The designer can configure certain parameters to adjust the CPU’s size, power, and performance. For example, the N9 core can be configured with 16 or 32 general registers, two or three read ports on the register file, one or two write ports, a fast or a small multiplier, a 24-bit or 32-bit address space, and different bus (APB, AHB, AHB-Lite, AXI) interfaces to connect to the rest of the system.